patch-2.1.44 linux/arch/sparc64/kernel/dtlb_miss.S

• Lines: 65
• Date: Mon Jul 7 08:18:54 1997
• Orig file: v2.1.43/linux/arch/sparc64/kernel/dtlb_miss.S
• Orig date: Mon Apr 14 16:28:08 1997

diff -u --recursive --new-file v2.1.43/linux/arch/sparc64/kernel/dtlb_miss.S linux/arch/sparc64/kernel/dtlb_miss.S
@@ -1,4 +1,4 @@
-/* $Id: dtlb_miss.S,v 1.11 1997/04/10 01:59:35 davem Exp $
+/* $Id: dtlb_miss.S,v 1.12 1997/06/26 12:47:08 jj Exp $
  * dtlb_miss.S:	Data TLB miss code, this is included directly
  *              into the trap table.
  *
@@ -19,9 +19,11 @@
  *		}
  *		goto longer_processing;
  * } else {
- *		if(fault_address >= KERNBASE &&
- *		   fault_address < VMALLOC_START) {
- *			tlb_load(__pa(fault_address) | PAGE_KERNEL);
+ *		if(fault_address >= PAGE_OFFSET) {
+ *			pte_val = PAGE_KERNEL;
+ *			if (fault_address & 0x10000000000)
+ *				pte_val = PAGE_KERNEL_IO;
+ *			tlb_load(__pa(fault_address) | pte_val);
  *			return_from_trap();
  *		} else {
  *			pgd = pgd_offset(swapper_pg_dir, fault_address);
@@ -32,9 +34,9 @@
  * This is optimized for user TLB misses on purpose.
  */
 
-#define KERN_HIGHBITS	(_PAGE_VALID | _PAGE_SZ4MB)
+#define KERN_HIGHBITS	((_PAGE_VALID | _PAGE_SZ4MB) ^ 0xfffff80000000000)
 #define KERN_LOWBITS	(_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
-#define KERN_LOWBITS_IO	(_PAGE_E | _PAGE_P | _PAGE_W)
+#define KERN_LOWBITS_IO	((_PAGE_E | _PAGE_P | _PAGE_W) ^ KERN_LOWBITS)
 
 				/* ICACHE line 1 */
   /*0x00*/	ldxa		[%g0] ASI_DMMU, %g1		! Get TAG_TARGET
@@ -57,17 +59,17 @@
 1:/*0x3c*/	retry							! Trap return
 
 3:				/* ICACHE line 3 */
-  /*0x40*/	sllx		%g1, 43, %g5		! This gets >= VMALLOC_START...
-  /*0x44*/	brlz,pn		%g5, 4f			! ...if now less than zero.
-  /*0x48*/	 andncc		%g1, 0x3ff, %g0		! Slick trick...
-  /*0x4c*/	be,pn		%xcc, 4f		! Yes, it is some PROM mapping
-  /*0x50*/	 srlx		%g5, 21, %g5		! This is now physical page
-  /*0x54*/	sethi		%uhi(KERN_HIGHBITS), %g1	! Construct PTE
-  /*0x58*/	sllx		%g1, 32, %g1			! Move priv bits up
-  /*0x5c*/	or		%g1, %g5, %g1			! Or in the page
+  /*0x40*/	sllx		%g1, 22, %g5			! This is now physical page + PAGE_OFFSET
+  /*0x44*/	brgez,pn	%g5, 4f				! If >= 0, then walk down page tables
+  /*0x48*/	 sethi		%uhi(KERN_HIGHBITS), %g1	! Construct PTE ^ PAGE_OFFSET
+  /*0x4c*/	andcc		%g3, 0x80, %g0			! Slick trick...
+  /*0x50*/	sllx		%g1, 32, %g1			! Move high bits up
+  /*0x54*/	or		%g1, (KERN_LOWBITS), %g1	! Assume not IO
+  /*0x58*/	bne,a,pn	%icc, 5f			! Is it an IO page?
+  /*0x5c*/	 xor		%g1, (KERN_LOWBITS_IO), %g1	! Aha, it is IO...
 
 				/* ICACHE line 4 */
-  /*0x60*/	or		%g1, (KERN_LOWBITS), %g1	! Set low priv bits
+5:/*0x60*/	xor		%g1, %g5, %g1			! Slick trick II...
   /*0x64*/	stxa		%g1, [%g0] ASI_DTLB_DATA_IN	! TLB load
   /*0x68*/	retry						! Trap return
 4:/*0x6c*/	ldxa		[%g0] ASI_DMMU_TSB_8KB_PTR, %g1	! For PTE offset
@@ -78,3 +80,4 @@
 
 #undef KERN_HIGHBITS
 #undef KERN_LOWBITS
+#undef KERN_LOWBITS_IO