patch-2.1.34 linux/arch/sparc64/kernel/itlb_miss.S

• Lines: 113
• Date: Fri Apr 11 10:47:36 1997
• Orig file: v2.1.33/linux/arch/sparc64/kernel/itlb_miss.S
• Orig date: Mon Mar 17 14:54:23 1997

diff -u --recursive --new-file v2.1.33/linux/arch/sparc64/kernel/itlb_miss.S linux/arch/sparc64/kernel/itlb_miss.S
@@ -1,71 +1,49 @@
-/* $Id: itlb_miss.S,v 1.5 1997/02/25 20:00:05 jj Exp $
+/* $Id: itlb_miss.S,v 1.10 1997/03/26 12:24:18 davem Exp $
  * itlb_miss.S:	Instruction TLB miss code, this is included directly
  *              into the trap table.
  *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  */
 
-	/* We are in the MMU globals, %g7 contains the physical
-	 * address of current->mm->pgd at all times.  %g2 is
-	 * also preloaded with the mask 0x1ff8 to make things
-	 * even quicker.
-	 *
-	 * Many subtle things are done here.  The high bits of
-	 * the virtual address missed are most easily obtained
-	 * from the tag target (it is at address zero in ASI_IMMU
-	 * so no address formation is necessary to get at this).
-	 * This is used to compute the pgd and pmd table offsets.
-	 *
-	 * Even more clever is that physical page zero is always
-	 * a page full of zeroes.  This means we can just follow
-	 * through with all the page table traversals even if nothing
-	 * is mapped because we'll just do loads from page zero
-	 * and get yet another zero.  We only need to do the check
-	 * for the valid bit being set in the final pte we obtain.
-	 *
-	 * Furthermore, we set the TSB base register to the address
-	 * zero, and we use the 8KB tsb ptr to calculate the pte
-	 * offset.  Again it is at address zero in ASI_IMMU_TSB_8KB_PTR
-	 * so no address formation is necessary, saves more instructions.
-	 *
-	 * We use physical address accesses to get at the page
-	 * tables, and this is for two reasons.  This makes it
-	 * impossible to take a fault while we are servicing the
-	 * miss.  Also this physical bypass access only allocates
-	 * in the E-cache, and thus we prevent D-cache pollution
-	 * from the miss handlers probing the page tables.
-	 *
-	 * It looks very hairy and slow.  But I take only 1 more
-	 * overhead of loads from ram than the Solaris version, and
-	 * my version is one instruction quicker for a true TLB miss.
-	 * And more importantly, all true TLB misses under Linux will be
-	 * serviced in _constant_ time.  When using the TSB in the
-	 * manner it was intended to be used (like solaris does) the
-	 * overhead for a TLB miss is _indeterminate_ especially during
-	 * processes startup when the TSB is cold.
-	 */
+/* Gratuitous comment. */
 
-	/* I-cache line 0 */
-	ldxa		[%g0] ASI_IMMU, %g1		! grab Tag Target
-	srlx		%g1, 8, %g3			! put high vaddr bits in place
-	and		%g3, %g2, %g3			! get offset
-	ldxa		[%g7 + %g3] ASI_PHYS_USE_EC, %g5! load pgd
-	sllx		%g1, 2, %g4			! begin pmd_offset formation
-	and		%g4, %g2, %g3			! and now mask it
-	ldxa		[%g5 + %g3] ASI_PHYS_USE_EC, %g4! load pmd
-	ldxa		[%g0] ASI_IMMU_TSB_8KB_PTR, %g1	! get 8KB pointer bits
-	/* I-cache line 1 */
-	srlx		%g1, 1, %g1			! shift right to get pte_offset
-	ldxa		[%g4 + %g1] ASI_PHYS_USE_EC, %g2! load pte
-	brlz,a,pt	%g2, 1f				! is valid bit clear?
-	 stxa		%g2, [%g0] ASI_ITLB_DATA_IN	! nope, load TTE into ITLB
+				/* ICACHE line 1 */
+  /*0x00*/	ldxa		[%g0] ASI_IMMU, %g1		! Get TAG_TARGET
+  /*0x04*/	srlx		%g1, 8, %g3			! Position PGD offset
+  /*0x08*/	srlx		%g1, 48, %g5			! Shift down CONTEXT bits
+  /*0x0c*/	and		%g3, %g2, %g3			! Mask PGD offset
+  /*0x10*/	sllx		%g1, 2, %g4			! Position PMD offset
+  /*0x14*/	ldxa		[%g0] ASI_IMMU_TSB_8KB_PTR, %g1	! For PTE offset
+  /*0x18*/	brz,pn		%g5, 3f				! Context 0 == kernel
+  /*0x1c*/	 and		%g4, %g2, %g4			! Mask PMD offset
 
-	ba,a,pt		%xcc, sparc64_itlb_refbit_catch	! longer processing needed
-1:
-	retry						! return from trap
+				/* ICACHE line 2 */
+  /*0x20*/	ldxa		[%g7 + %g3] ASI_PHYS_USE_EC, %g5	! Load user PGD
+  /*0x24*/	srlx		%g1, 1, %g1				! PTE offset
+  /*0x28*/	ldxa		[%g5 + %g4] ASI_PHYS_USE_EC, %g3	! Load PMD
+2:/*0x2c*/	ldxa		[%g3 + %g1] ASI_PHYS_USE_EC, %g5	! Load PTE
+  /*0x30*/	brlz,a,pt	%g5, 1f					! Valid set?
+  /*0x34*/	 stxa		%g5, [%g0] ASI_ITLB_DATA_IN		! TLB load
+  /*0x38*/	ba,a,pt		%xcc, sparc64_itlb_refbit_catch		! Nope...
+1:/*0x3c*/	retry							! Trap return
 
-	nop; nop;
-	/* I-cache line 2 */
-	nop; nop; nop; nop; nop; nop; nop; nop;
-	/* I-cache line 3 */
-	nop; nop; nop; nop; nop; nop; nop; nop;
+3:				/* ICACHE line 3 */
+  /*0x40*/	ldxa		[%g6 + %g3] ASI_PHYS_USE_EC, %g5	! Load kern PGD
+  /*0x44*/	srlx		%g1, 1, %g1				! PTE offset
+  /*0x48*/	ba,pt		%xcc, 2b				! Continue above
+  /*0x4c*/	 ldxa		[%g5 + %g4] ASI_PHYS_USE_EC, %g3	! Load PMD
+  /*0x50*/	nop
+  /*0x54*/	nop
+  /*0x58*/	nop
+  /*0x5c*/	nop
+
+				/* ICACHE line 4 */
+  /*0x60*/	nop
+  /*0x64*/	nop
+  /*0x68*/	nop
+  /*0x6c*/	nop
+  /*0x70*/	nop
+  /*0x74*/	nop
+  /*0x78*/	nop
+  /*0x7c*/	nop